The present invention relates in general to the field of integrated circuit packages with multiple power supplies and more specifically to enabling greatly improved chip power bonding flexibility in systems integrating multiple complex functions to produce high functional density in compact electronic systems having high operational performance levels.
An example of conventional integrated circuits and packages used in a conventional system with multiple power supplies (multi-power product) is an ordinary PC. Recent developments in highly compact, portable electronics may incorporate ICs in packages that have multiple functions requiring two or more different power supply leads or contacts for connection to electrically isolated or independent system power supplies. Industry today uses a mixed set of nomenclature designating IC packages with multiple and/or independent power supplies. Some of these are xe2x80x9cmulti-power levelxe2x80x9d, xe2x80x9cmulti-voltage levelxe2x80x9d. For the purposes of this discussion the term xe2x80x9cmulti-power chipxe2x80x9d is used to designate a single IC chip/package having multiple functions that require multiple independent and/or electrically isolated power supply voltages (two or more, not counting ground return). These multiple voltages are provided by package electrical connections, i.e. power supply leads (conductive pads, pins or wires for mounting on a printed circuit board or substrate) for supplying different power supply voltages to internal functions separated or electrically isolated from each other.
Conventional IC packages preferred for such compact, portable electronic systems include those known as mini-BGA, micro-BGA, Flex-BGA, flip-chip-BGA, Film BGA, BCC, TFBGA and the like. Known examples are described by Schueller et al in U.S. Pat. No. 5,990,545, xe2x80x9cChip Scale Ball Grid Array for Integrated Circuit Packagexe2x80x9d the xe2x80x3545 patent), by Eng et al in U.S. Pat. No. 5,952,611 xe2x80x9cFlexible Pin Location Integrated Circuit Packagexe2x80x9d (the xe2x80x3611 patent), and by Igarashi et al in U.S. Pat. No. 5,990,546 xe2x80x9cChip Scale Package Type of Semiconductor Devicexe2x80x9d (the xe2x80x3546 patent), all incorporated herein by reference. The packages detailed in these patents described some of the known structural features for connecting external system power supply lines to the package external leads, and different organization, structure and formation of internal package insulating layers and conductive routing elements to provide a desirable arrangement of numerous isolated conductor paths to internal package bonding lands for subsequent convenient connection to selected chip bonding pads.
For example the xe2x80x3546 patent shows chip electrode 11 (i.e. a chip bonding pad) coupled to an outer electrode 22 of the package through contact with a metallic bump 211 forming the inner end of inner electrode 21. The inner electrode 21 is one end of a metal routing conductor 23 extending between insulating layers 24 and 25 and electrically connects outer electrode 22 to inner package electrode 21.
Many techniques for forming arrangements of insulated routing conductors between inner package electrodes and outer package electrodes are known and are not part of the present invention. However, previously, conventional integrated circuit packages for systems attempting to integrate several or many disparate functions into a few packages or a single package present a number of chronic difficulties for the electronics industry. These difficulties are exaggerated especially in the area of attempting to integrate what previously have been separate functions into unitary or single modules. E.g. mobile phones containing one or more other functions: fax, messaging, microcomputer, personal digital assistants (PDAs) and the like.
To produce a single-chip system with multiple, disparate functions, such as a mobile phone combined for example with some computational capability, it may be necessary to combine RF power, analog processing, semiconductor RAM/ROM and CPU functions and perhaps flash memory. Each of these functions may work optimally at different power supply voltage levels, e.g., perhaps 10 volts for flash memory, 5 volts for the phone""s RF transmitter and 3 volts for the RAM/ROM and 1.9 volts or less for the CPU.
Real world examples of these in particular include: single package memory subsystems with 3.3 v and 5 v power supply leads. Another single package solution is an entire PC having power supply voltages of 1.8 v (CPU), 3 v (memory), 5 v (logic) and 10 v (embedded flash memory).
The problems known in packaging multi-functional, multi-power level systems include power, ground, and I/O package pin count proliferation, the many-to-one relationship between chip power pads and multiple system power bus circuits (power bus nets), difficulty in reconciling chip bonding pad and package bonding area layouts with functional architecture, bonding ease, manufacturing throughput and cost, system board layout constraints, operating performance levels, signal transition speeds, lead inductance, I/O driver noise (ground bounce), signal cross-coupling, signal isolation, and others.
Power efficiency is a phrase sometimes used to indicate the degree to which the power requirements for the chip or die inside the package, are met by the available package pins (either the number of package pins or package lead count) or the topological placement of the internal package electrodes used as package electrode bonding areas (lands) relative to the chip bonding locations (pads). A typical example of some of these difficulties in the case of a multi-power IC chip with three different functions each requiring an independent power supply that is to be connected to a PC board system having 3 electrically isolated power supplies V1, V2 and V3 are shown with regard to FIG. 7.
In FIG. 7, there is shown an example of preliminary bonding diagram 700 for multi-power IC chip 702 mounted in a prior art BGA package indicated by the arrow 700. The BGA package 700 has 256 bonding lands arranged as 2 opposed rows and 2 opposed columns along the periphery of the package 700 and indicated by arrows 706. 64 package bonding lands are arranged on each side of the package 700 and disposed to receive one end of a respective wire bond 744 connected at its other end to a respective chip bonding pad disposed on an adjacent chip edge.
The multi-power chip 702 has three separated or isolated power supply networks (nets) 710, 720 and 730. Four linear arrays of spaced apart chip bonding pads are arranged, one along each respective side of the nearly square chip 702 and indicated by arrows 740 pointing to two opposed rows and two opposed columns of chip bonding pad.
The chip 702 layout also includes chip signal traces (with associated bonding pads, not shown) connecting to a majority of the chip bonding pads 740. The chip bonding pads comprise two major groups: chip signal bonding pads, e.g. pads 746, and chip power bonding pads (CPpads). CPpads for the chip 702 are pads 711-715, 721-724, and 731-734.
Each of the power nets 710, 720 and 730 are connected to several particular chip power bonding pads selected from chip pads among the rows and columns 740 along each side of the chip 702. Specifically, power net 710 is connected to particular chip power bonding pads 711, 712, 713 and 715. Power net 720 is connected to particular chip power bonding pads 721, 722, 723 and 724. Power net 730 is connected to particular chip power bonding pads 731, 732, 733 and 734.
In this example, which is not a typical, the BGA package 700 was selected for a trial bonding diagram for mounting chip 702 because of size constraints imposed by the system for which the multi-power functions provided by chip 702 are intended. The board foot print for the 256 pin BGA package 700 is defined by package length 750 and package width 752.
Although the package 700 meets the footprint requirement for the system, and can accept the chip 702 having chip length 756 and width 758 being mounted within, it can be seen that some of the chip power bonding pads are not connected to any one of the package bonding lands i.e. chip power pads 712, 722, 734 between package bonding lands 193-256, chip power pads 713, 714, 732 along package bond lands 129-192 and chip power pads 715, 721, 733 between package bonding lands 64 and 65.
Generally, it is preferred that the multiple chip power bonding pads for each chip power net be distributed roughly equally around the chip periphery 742 to provide similar low resistance paths to the associated system power supplies and system ground or grounds (e.g., V1, V2 and V3) for circuit functions distributed around the chip 702 as shown. The majority of connections (in this case wire bonds 744) between chip 702 and the package 700 are system signals (e.g. I/O) between respective chip signal bonding pads, and package signal bonding lands e.g., chip pad 746 and package signal bonding land 748. In order for the chip 702 to be fully functional, each and every chip signal must be connected to a package signal bonding land.
Therefore, after all the chip signal bonding pads 740 are connected to a respective one of the package bonding lands 706, there are no available package bonding lands to connect to the remaining chip bonding pads, 715, 721, 733, 714, 732, 713, 712, 722 and 734. This is precisely the dilemma often presented to designers of compact, high-density systems utilizing multi-power IC chips. In order to provide complete functionality, some power chip pads must be left unconnected, or a package having more package bonding lands, and consequently a much larger footprint must be used. Frequently system size constraints would prohibit using larger packages. This can force one to make one of several extremely undesirable decisions: abandon the product, redesign the system architecture and use different and perhaps new functions, or redesign the chips to fit in the available package outlines.
One or more of the manufacturing, functional and operational performance requirements placed on chip-package combination in the multi-power system 700 typically result in a requirement for more than a single chip power bonding pad (Cppad) for each of the separate power nets 710, 712, 714 for connection to V1, V2 and V3 respectively.
The number and location of CPpad connections demanded or required by desired chip functionality or performance vary. The width, length and location of chip power traces are limited by the necessary on-chip circuitry and the available die area. Multiple chip power traces may be necessary to feed on or more ones of particular on-chip circuit function or functions widely separated on the chip layout to obviate potential voltage drop along a power bus trace connecting such widely separated functions. Alternatively, multiple chip power traces may be necessary to decouple power bus to signal line cross talk. Or additional chip power traces may be required for electrical shielding or isolation between adjacent analog and digital circuit functions. The number and location of on-chip signal traces (cstrace) and their associated chip signal bonding pads (CSpads) frequently compete with the number, availability and location of the Ppads relative to the desired number and locations of chip power pads.
The chip designer typically wants to optimize chip circuit function and performance while simultaneously minimizing chip area and package area (footprint). The chip designer will prefer to physically locate chip functions in the package in a way that maximizes the performance of the most desired system features, whether it be switching speed, operating frequency, noise immunity and the like. Therefore the designer will tend to fashion a chip plan focusing on those aspects. Once the chip functions and performance requirements are defined and located, chip circuitry power connections must be made between the chip functions and the required system power bus(es). Connection of the Chip power pads to PPads frequently are constrained by the number and locations of CSpads and the number and locations of available PPads. So an undesirable tradeoff must frequently be made between chip (and consequently, system) performance and the size and cost of the package in which the chip is mounted.
There are many instances of systems produced that are larger or more costly than otherwise desired because the package in which chips are mounted is selected only because there are enough package pins (and PPads) to accommodate all the chip signals and just enough to accommodate the number of chip power nets. If an smaller alternate package had been available, that could accommodate the number and location of all chip signal pads and all desired chip power pads, the system could have been smaller and/or less costly and perhaps provided higher performance.
This illustrates the need for a package having a package bonding pad(s) (or bonding location) PPad to be located and available, corresponding to where each and every desired chip power pad CPad is located for a given chip function layout. Additionally, the chip layout may be such that there are conflicts between the optimum location of one or more chip power pads relative to other power pads or signal pads, and the available PC board or substrate connection pattern. One well-known problem is the double-sided PC board pin 1 power/ground contention issue.
All chip signal pads (CSpads) must have corresponding package signal pads (pspads) in order to provide connection to respective external system signals. Because of the limited number of package bonding pads (ppads) available caused by limitations on pad size, spacing and package dimensions, caused by cost or system size limitations, some chip power pads may not have corresponding package power pads. This could result in limited or lowered operational performance, lower yield and higher cost.
Frequently a system redesign or feature addition will result in an additional signal being added to the chip. This means there must be a package bonding land available for bonding to the new signal pad being added to the chip layout. If the package is already pin limited, the package size may have to be increased just to add one additional pin. If the PC board layout were also size constrained, this would mean a complete system redesign; qualification and new manufacturing set up would be necessary just to release the new product feature. This is not an acceptable situation in most cases.
In the particular case shown in FIG. 7 if chip power pads for chip power bus 710 dont have corresponding package power pads to accept bond wires, they must be left unconnected in order to make the chip 702 functional at all. Therefore, power distribution from the system power bus on the PC board or substrate (not shown) intended to provide power for the chip power bus 710 and thence to the appropriate chip circuit functions (not shown) may not be sufficiently uniform to permit the chip 702 to meet operational or performance requirements. This can occur if the power drawn by circuit functions adjacent to the un-bonded cpads is large relative to the total current capacity of the chip power bus 710.
To maximize system performance the current carrying capability or capacity of the total power distribution path of each power bus must be optimized. The total power distribution path for the whole package-chip combination consists of the package pins, bonding wires, package bonding pads (ppads), chip bonding pads (cpads) and the on-chip power traces to all the on-chip circuit-to-power bus connections. In other words the total conductive path(s) between one end of the power bus at the package pin power bus connections to the PC board outside, and the innermost chip circuitry connections to the other end(s) that power bus distribution must be carefully considered.
Another aspect of a power efficiency limitation for the prior art is the current carrying capacity of bonding wires relative to the circuit traces. Circuit traces are very narrow and thus have limited current capacity. A single bonding wire of 1 mil can supply about 20 to 40 ma of current. A single circuit trace to carry that much current may have to be many mils wide. If the circuitry on the chip that needs that much current is not conveniently located relative to an available package power pad, much chip area is wasted just in metal width, unless additional package pins are dedicated to distribute that current to widely separated points on the chip. This wasted chip area leads to higher cost and lower yields.
These issues are aggravated by the small packaging formats, e.g. chip scale packages such as mini-BGA, micro-BGA, Flex BGA, flip-chip BGA, film BGA, BCC, TFBGA and the like, desired in high integration systems and are further aggravated by the expanded set of functional and performance requirements imposed by the combination of functions seen in more complex systems.
Other issues exacerbating the dilemma are characteristics like: package size, package lead self-resistance, self-inductance, mutual-inductance, cross talk to other signal or power bus lines or traces, isolation between adjacent circuit functions having contiguous peripheral edges on the chip.
It is not only the amount of current being provided to a particular circuit function(s), it is the parasitic elements associated with that delivery because the size and number of chip circuit traces that are connected to chip power pads dont match the desired level: e.g. resistance, impedance, inductance, shielding, isolation, etc. as listed above.
These issues are particularly relevant to systems-on-a-chip like a mobile phone, desktop or notebook computer, because the more different types of functions there are being integrated into one package, the more likely there are different power level requirements. E.g., a memory function in one part of the chip, RF transmission in another part, etc.
The present invention has been made in view of the above circumstances, and objects and advantages of the present invention are:
easily provide many-to-one and one-to-many relationship between selected multiple external package power leads and selected internal multiple chip power net bonding pads;
provide improved flexibility in selecting bonding arrangements for electrical connection between multiple external package power leads and corresponding chip power net bonding pads;
provide improved flexibility in bonding between package signal bonding lands and chip signal bonding pads.
provide an integrated circuit package for multi-power supply IC chips capable of maximizing chip bonding pad count,
provide an integrated circuit package for multi-power supply IC chips capable of minimizing package pin count,
provide an integrated circuit package for multi-power supply IC chips capable of minimizing chip area for a given chip power net bonding pad count;
provide an integrated circuit package for multi-power supply IC chips capable of minimizing package footprint;
provide an integrated circuit package for multi-power supply IC chips capable of providing improved chip-to-package bonding layout flexibility;
provide an integrated circuit package for multi-power supply IC chips capable of and providing improved package-to-board mounting layout flexibility;
It is another object of the present invention to provide a multi-power supply integrated circuit package having improved flexibility in system function integration while retaining high levels of system function performance.
It is still another object of the present invention to provide a circuit system having high functional density and high performance including a scalable multi-power supply chip scale integrated circuit package.
It is yet still another object of the present invention to provide an integrated circuit package system capable of minimizing package footprint for a high functional density multipower integrated circuit.